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datasheet 15-output low power differential zbuffer for pcie gen3 and qpi 9ZXL1530 idt? 15-output low power differential zbuffer for pcie gen3 and qpi 1 9ZXL1530 rev c 031312 description the 9ZXL1530 is a 15-output version of the intel db1900z differential buffer utilizing low-power hcsl (lp-hcsl) outputs to reduce power consumption more than 50% from the original idt9zx21501. it is suitable for pci-express gen3 or qpi applications, and uses a fixed external feedback to maintain lo w drift for demanding qpi applications. the part is backwards compatible to pcie gen1 and gen2. recommended application 15-output low power differential z-buffer for pcie gen3 and qpi key specifications ? cycle-to-cycle jitter: < 50ps ? output-to-output skew: <65ps ? input-to-output delay: fixed at 0 ps ? input-to-output delay variation: <50ps ? phase jitter: pcie gen3 < 1ps rms ? phase jitter: qpi 9.6gb/s < 0.2ps rms features/benefits ? fixed feedback path; 0ps input-to-output delay ? 9 selectable smbus addresse s; multiple devices can share same smbus segment ? separate vddio for outputs; allows maximum power savings ? pll or bypass mode; pll can dejitter incoming clock ? selectable pll bw; minimizes jitter peaking in downstream pll's ? spread spectrum compatible; tracks spreading input clock for emi reduction ? smbus interface; unused outputs can be disabled ? 100mhz & 133.33mhz pll mode; legacy qpi support ? differential outputs are low/low in power down; maximum power savings output features ? 15 - lp-hcsl differential output pairs block diagram logic dif(14:0) hibw_bypm_lobw# smbdat smbclk ckpwrgd/pd# smb_a0_tri smb_a1_tri 100m_133m# z-pll (ss compatible) fbout_nc dif_in dif_in#
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 2 9ZXL1530 rev c 031312 pin configuration power management table power connections functionality at power-up (pll mode) pll operating mode tri-level input thresholds gnd vddio dif_14# dif_14 dif_13# dif_13 vdd gnd dif_12# dif_12 dif_11# dif_11 gnd vddio dif_10# dif_10 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vd da 1 48 vddio gn da 247 gnd 100m_133m# 346 dif_9# hibw_bypm_lobw# 4 45 dif_9 ckpwrgd_pd# 544 dif_8# gnd 643 dif_8 vddr 742 gnd dif_in 841 vdd dif_in# 940 dif_7# smb_a0_tri 10 39 dif_7 smbdat 11 38 dif_6# smbclk 12 37 dif_6 smb_a1_tri 13 36 vddio fbout_nc# 14 35 gnd fbout_nc 15 34 dif_5# gnd 16 33 dif_5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 dif_0 dif_0# vddio gnd dif_1 dif_1# dif_2 dif_2# gnd vd d dif_3 dif_3# dif_4 dif_4# vddio gnd note: pins with ^ prefix have internal 120k pullup pins with v prefix have internal 120k pulldowm 9ZXL1530 control bits ckpwrgd_pd# dif _ in/ dif_in# smb us en bit dif _x / dif_x# fbout _ nc/ fbout_nc# 0 x x low /low low/low off 0 low /low running on 1 running running on inputs pll state 1 running outputs vdd vddio gnd 1 2 analog pll 7 6 analog input 26, 41, 58 19,31,36,48,51 ,63 16,20,25,32,3 5,42,47,52,57 ,64 d if clocks pin n umbe r description 100m_133m# dif_in (mhz) difx (mhz) 1 100.00 dif_in 0 133.33 dif_in hibw_b ypm_lobw# byte0, bit (7:6) low ( pll low bw) 00 mid (bypass) 01 high (pll high bw) 11 note: pll is off in bypass mode level voltage low <0.8v mid 1.2 2.2v
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 3 9ZXL1530 rev c 031312 pin descriptions pin # pin name type description 1 vdda pwr 3.3v power for the pll core. 2 gnda pwr ground pin for the pll core. 3 100m_133m# in 3.3v input to select operating frequency see functionality table for definition 4 hibw_bypm_lobw# in trilevel input to select high bw, bypass or low bw mode. see pll operating mode table for d etails. 5ckpwrgd_pd# in n otif ies device to sample latched inputs and start up on first high assertion, or exit power down mode on subsequent assertions. low enters power d own mode. 6 gnd pwr ground pin. 7vddr pwr 3.3v power for differential input clock (receiver). this vdd should be t reated as an analog power rail and filt ered appropriately. 8 dif_in in 0.7 v differential true input 9 dif_in# in 0.7 v differential com p lementar y in p ut 10 smb_a0_tri in smbus address bit. this is a tri-level input that w orks in conjunction with the smb_a1 to decode 1 of 9 smbus addresses. 11 smbdat i/o d ata p in o f sm bus circu itr y , 5v tolerant 12 smbclk in c lock p in of smbu s circuit r y , 5v tolerant 13 smb_a1_tri in smbus address bit. this is a tri-level input that w orks in conjunction with the smb_a0 to decode 1 of 9 smbus addresses. 14 fbout_nc# out c omplementary half of differential feedback output. this pin should not be connected to anything outside t he chi p . it exists to p rovide dela y p ath matchin g to g et 0 p ro p a g ation dela y . 15 fbout_nc out true half of differential feedback output. this pin should not be connected to anything outside t he chip. it exists to p rovide dela y p ath matchin g to g et 0 p ro p a g ation dela y . 16 gnd pwr ground p in. 17 dif_0 ou t 0.7v differential true clock out p ut 18 dif_0# ou t 0.7v differential complementary clock output 19 vddio pwr power supply for differential outputs 20 gnd pwr ground pin. 21 dif_1 ou t 0.7v differential true clock output 22 dif_1# ou t 0.7v differential complementary clock output 23 dif_2 ou t 0.7v differential true clock output 24 dif_2# ou t 0.7v differential complementary clock output 25 gnd pwr ground pin. 26 vdd pwr power supply, nominal 3.3v 27 dif_3 ou t 0.7v differential true clock output 28 dif_3# ou t 0.7v differential complementary clock output 29 dif_4 ou t 0.7v differential true clock output 30 dif_4# ou t 0.7v differential complementary clock output 31 vddio pwr power supply for differential outputs 32 gnd pwr ground pin.
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 4 9ZXL1530 rev c 031312 pin descriptions (cont.) pin # pin name type description 33 dif_5 out 0.7v differential true clock output 34 dif_5# out 0.7v differential complementary clock output 35 gnd pwr ground pin. 36 vddio pwr power supply for differential outputs 37 dif_6 out 0.7v differential true clock output 38 dif_6# out 0.7v differential complementary clock output 39 dif_7 out 0.7v differential true clock output 40 dif_7# out 0.7v differential complementary clock output 41 vdd pwr power supply, nominal 3.3v 42 gnd pwr ground pin. 43 dif_8 out 0.7v differential true clock output 44 dif_8# out 0.7v differential complementary clock output 45 dif_9 out 0.7v differential true clock output 46 dif_9# out 0.7v differential complementary clock output 47 gnd pwr ground pin. 48 vddio pwr power supply for differential outputs 49 dif_10 out 0.7v differential true clock output 50 dif_10# out 0.7v differential complementary clock output 51 vddio pwr power supply for differential outputs 52 gnd pwr ground pin. 53 dif_11 out 0.7v differential true clock output 54 dif_11# out 0.7v differential complementary clock output 55 dif_12 out 0.7v differential true clock output 56 dif_12# out 0.7v differential complementary clock output 57 gnd pwr ground pin. 58 vdd pwr power supply, nominal 3.3v 59 dif_13 out 0.7v differential true clock output 60 dif_13# out 0.7v differential complementary clock output 61 dif_14 out 0.7v differential true clock output 62 dif_14# out 0.7v differential complementary clock output 63 vddio pwr power supply for differential outputs 64 gnd pwr ground pin.
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 5 9ZXL1530 rev c 031312 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9ZXL1530. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical pa rameters are guaranteed only over the recommended operating temperature range. electrical characteristi cs?clock input parameters parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda, r 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 i/o supply voltage vddio 4.6 v 1,2 i nput low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsm b smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 ju nction temp erature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduct ion. 2 o p eration under these conditions is neither im p lied nor g uaranteed. ta = t com ; supply voltage vdd/vd da = 3.3 v +/-5%, vddio = 1.05 to 3.3v +/-5%. see test loads for loading c onditions parameter symbol conditions min typ max units notes input h igh voltage - dif_in v ihd if differential inputs ( sin g le-ended measurement ) 600 800 1150 mv 1 input low voltage - d if_in v il dif differential inputs ( sin g le-ended measurement ) v ss - 300 0300mv1 i nput c ommon mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - d if_in v swing pea k t o pe ak va lue 30 0 1 450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty c ycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j dif in differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured throu g h +/-75mv window centered around differential zero
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 6 9ZXL1530 rev c 031312 electrical characteristics?input/ supply/common output parameters ta = t com ; supply voltage vdd/vd da = 3.3 v +/-5%, vddio = 1.05 to 3.3v +/-5%. see test loads for loading c onditions parameter symbol conditions min typ max units notes ambient operating tem p erature t com c ommmercial range 0 70 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level in p uts 2 v dd + 0.3 v1 i nput low voltage v il single-ended inputs, except smbus, low threshold and tri-level in p uts gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i in p sin gle -e nded inp uts v in = 0 v; inputs with internal pull-up resistors v in = vdd; input s w ith internal pull-down resistors -200 200 ua 1 f ibyp v dd = 3.3 v, bypass mode 33 150 mhz 2 f ip ll v dd = 3.3 v, 100mhz pll mode 90 100.00 110 mhz 2 f ip ll v dd = 3.3 v, 1 33.33 mhz pl l mode 120 133.33 147 mhz 2 pin i nductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c in dif _in dif_in diff erential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 c lk sta bilization t stab from v dd pow er-up and after input clock stabilization or de-assertion of pd# to 1st clock 1ms1,2 input ss modulation frequency f mod in allowable frequency (triangular modulation) 30 33 khz 1 tdrive_pd# t drvpd dif outp ut en able afte r pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 5 ns 1,2 trise t r r ise time of control inputs 5 ns 1,2 smbus input low voltage v il smb 0.8 v 1 smbus input high voltage v ihsm b 2.1 v dd smb v1 smbus output low voltage v ol s mb @ i pu llu p 0.4 v 1 smbus sink current i pul lup @ v ol 4ma1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operat ing frequen cy f minsm b minimum smbus operating frequency 100 khz 1,5 1 guaranteed b y desi g n and characterization, not 100% tested in p roduct ion. 2 control in p ut must be monotonic from 20% to 80% of in p ut swin g . 5 the differential input clock must be running for the smbus to be active input current 3 time from deassertion until outputs are >200 mv 4 dif_in input capacitance inpu t fre quen cy
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 7 9ZXL1530 rev c 031312 electrical characteristics?dif 0.7v low power differential outputs electrical characterist ics?current consumption ta = t com ; supply voltage vdd/vd da = 3.3 v +/-5%, vddio = 1.05 to 3.3v +/-5%. see test loads for loading c onditions parameter sym bol conditions min typ max u nits notes slew rate trf scope averaging on 1 3 4 v/ns 1, 2, 3 slew rate matching trf slew rate matching. 7.6 20 % 1, 2, 4 voltage high vhigh 660 757 850 1 voltage low vlow -150 16 150 1 max voltage vmax 857 1150 1 min voltage vmin -300 -36 1 vsw ing vswing scope averaging off 300 mv 1, 2 crossing voltage (abs) vcross_abs scope averaging off 300 469 550 mv 1, 5 crossing voltage (var) -vcross scope averaging off 14 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. n ote that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross t o be smaller than vcross absolute. mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. c l = 2pf with r s = 2 7 ? for zo = 85 ? differential trace impedance. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for c lock#. it is measured using a +/-75mv window centered on the average cross point where c lock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). ta = t com ; supply voltage vdd/vd da = 3.3 v +/-5%, vddio = 1.05 to 3.3v +/-5%. see test loads for loading c onditions parameter symbol conditions min typ max units notes i ddvdd all outputs active @100mhz, c l = 2p f; 23 40 ma 1 i ddvdda/r all outputs active @100mhz, c l = 2p f; 15 20 ma 1 i ddvddio all outputs active @100mhz, c l = 2p f; 124 150 ma 1 i ddvddpd all differential pairs low-low 2.2 4 ma 1 i ddvdda/rpd all differential pairs low-low 4.9 7 ma 1 i ddvddiopd all differential pairs low-low 0.16 0.5 ma 1 1 guaranteed b y desi g n and characterization, not 100% test ed in p roduction. operating supply current powerdown current
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 8 9ZXL1530 rev c 031312 electrical characteristics?skew and differential jitter parameters ta = t com ; supply voltage vdd/vdda = 3.3 v +/-5%, vddio = 1.05 to 3.3v +/-5%. see test loads for loading conditions parameter symbol conditions min typ max units notes clk_in, dif[x:0] t spo_pll input-to-output skew in pll mode nominal value @ 25c, 3.3v -100 -44 100 ps 1,2,4,5,8 clk_in, dif[x:0] t pd_byp input-to-output skew in bypass mode nominal value @ 25c, 3.3v 2.5 3.6 4.5 ns 1,2,3,5,8 clk_in, dif[x:0] t dspo_pll input-to-output skew varation in pll mode across volta g e and temperature -50 -2 50 ps 1,2,3,5,8 clk_in, dif[x:0] t dspo_byp input-to-output skew varation in bypass mode across temperature for a given voltage -250 250 ps 1,2,3,5,8 clk_in, dif[x:0] t dte random differential tracking error beween two 9zx devices in hi bw mode 35 ps (rms) 1,2,3,5,8 clk_in, dif[x:0] t dsste random differential spread spectrum tracking error beween two 9zx devices in hi bw mode 15 75 ps 1,2,3,5,8 dif{x:0] t skew_all output-to-output skew across all outputs (common to bypass and pll mode) 45 65 ps 1,2,3,8 pll jitter peaking j p eak-hibw lobw#_bypass_hibw = 1 0 1.75 2.5 db 7,8 pll jitter peaking j p eak-lobw lobw#_bypass_hibw = 0 0 0.75 2 db 7,8 pll bandwidth pll hi bw lobw#_bypass_hibw = 1 2 3.33 4 mhz 8,9 pll bandwidth pll lobw lobw#_bypass_hibw = 0 0.7 1.18 1.4 mhz 8,9 duty cycle t d c measured differentially, pll mode 45 50.4% 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -2 0 2 % 1,10 pll mode 24 50 ps 1,11 additive jitter in bypass mode 0 50 ps 1,11 notes for preceding table: 6. t is the period of the input clock 7 measured as maximum pass band g ain. at frequencies within the loop bw, hi g hest point of ma g nification is called pll jitter peakin g . 8. guaranteed by desi g n and characterization, not 100% tested in production. 9 measured at 3 db down or half power point. 10 duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in by pass mode. 11 measured from differential waveform 3 all bypass mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it. 4 this parameter is deterministic for a given device 5 measured with scope averaging on to find mean value. jitter, cycle to cycle t jcyc-cyc 1 measured into fixed 2 pf load cap. input to output skew is measured at the first output edge following the corresponding inp ut. 2 measured from differential cross-point to differential cross-point. this parameter can be tuned with external feedback path, if present.
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 9 9ZXL1530 rev c 031312 electrical characteristi cs?phase jitter parameters ta = t com ; supply voltage vdd/vdda = 3.3 v +/-5%, vddio = 1.05 to 3.3v +/-5%. see test loads for loading conditions parameter symbol conditions min typ max units notes t jp hpcieg1 pcie gen 1 30.1 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 1.0 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 1.7 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.38 1 ps (rms) 1,2,4 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.18 0.5 ps (rms) 1,5 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.13 0.3 ps (rms) 1,5 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.10 0.2 ps (rms) 1,5 t jp hpcieg1 pcie gen 1 0.00 10 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.01 0.3 ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.00 0.7 ps (rms) 1,2,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.00 0.3 ps (rms) 1,2,4,6 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.12 0.3 ps (rms) 1,5,6 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.00 0.1 ps (rms) 1,5,6 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.00 0.1 ps (rms) 1,5,6 1 applies to all outputs. 6 for rms figures, additive jitter is calculated by solving the following equation: (additive jitter)^2 = (total jittter)^2 - (i nput jitter)^2 5 calculated from intel-supplied clock jitter tool v 1.6.4 t jphqpi_smi phase jitter, pll mode t jphpcieg2 additive phase jitter, bypass mode t jphpcieg2 t jphqpi_smi 2 see http://www.pcisig.com for complete specs 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4 subject to final ratification by pci sig.
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 10 9ZXL1530 rev c 031312 test loads clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs with spread spectrum enabled differential output terminations dif zo ( ? )rs ( ? ) 100 33 85 27 differential zo, 10 inches lp-hcsl differential output 9zxl differential test loads rs rs 2pf 2pf 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm pe riod nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2,3 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2,4 ss c off center freq. mhz dif measurement window units notes 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm pe riod nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2,4 notes: 1 guaranteed by design and characterization, not 100% tested in production. 3 driven by src output of main clock, 100 mhz pll mode or bypass mode 4 driven by cpu output of main clock, 133 mhz pll mode or bypass mode measurement window units ssc on center freq. mhz 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck420bq/c k410b+ acc uracy requirements (+/-100ppm). the 9ZXL1530 itself does not contribute to ppm error. dif notes
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 11 9ZXL1530 rev c 031312 general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 12 9ZXL1530 rev c 031312 9ZXL1530 smb us addressing smb_a(1:0)_tri a ddress (rd/wrt bit = 0) (hex) 00 d8 0m da 01 de m0 c2 mm c4 m1 c6 10 ca 1m cc 11 ce smbustable: pll mode, and frequency select re g ister pin # name control function type 0 1 default bit 7 pll mode 1 pll operating mode rd back 1 r latch bit 6 pll mode 0 pll operating mode rd back 0 r latch bit 5 1 bit 4 dif_14_en output enable rw low/low enable 1 bit 3 dif_13_en output enable rw low/low enable 1 bit 2 0 bit 1 0 bit 0 100m_133m# fre q uenc y select readback r 133mhz 100mhz latch smbustable: output control re g iste r pin # name control function type 0 1 default bit 7 d if_5_en output enable rw low/low enable 1 bit 6 1 bit 5 d if_4_en output enable rw 1 bit 4 d if_3_en output enable rw 1 bit 3 d if_2_en output enable rw 1 bit 2 d if_1_en out p ut ena ble rw 1 bit 1 d if_0_en out p ut ena ble rw 1 bit 0 1 smbustable: output control registe r pin # name control function type 0 1 default bit 7 dif_12_en out p ut enable rw low/low enable 1 bit 6 dif_11_en out p ut ena ble rw 1 bit 5 dif_10_en out p ut ena ble rw 1 bit 4 1 bit 3 d if_9_en out p ut ena ble rw 1 bit 2 d if_8_en out p ut ena ble rw 1 bit 1 d if_7_en out p ut ena ble rw 1 bit 0 d if_6_en output enable rw 1 smb ustable: reserved re g ister pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved reserved reserved reserved 39/40 45/46 3 byte 1 43/44 byte 2 39/40 byte 0 4 4 61/62 59/60 21/22 17/18 55/56 37/38 29/30 29/30 23/24 53/54 49/50 byte 3 see pll operating mode readback table reserved reserved reserved reserved reserved reserved reserved reserved reserved low/low enable reserved
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 13 9ZXL1530 rev c 031312 smbustable: reserved register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbustable: vendor & revision id register pin # name control function t yp e0 1default bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbustable: device id pin # name control function t yp e0 1default bit 7 r1 bit 6 rx bit 5 rx bit 4 rx bit 3 rx bit 2 r0 bit 1 r0 bit 0 r1 smbustable: byte count register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 r w 1 bit 2 bc2 r w 0 bit 1 bc1 rw 0 bit 0 bc0 r w 0 smbustable: reserved register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved reserved reserved reserved reserved reserved reserved - b y te 5 - b y te 6 - - - - - - b y te 4 - - - - reserved reserved reserved reserved - reserved - reserved reserved reserved reserved reserved writing to this register configures how many bytes will be read back. - device id 0 default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. 1530 is 153 decimal or 99 hex device id 7 (msb) reserved device id 5 device id 6 - device id 3 - - - b y te 7 device id 2 device id 1 device id 4 revision id b rev = 0001 reserved vendor id b y te 8 - -
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 14 9ZXL1530 rev c 031312 common r ecommendations for differential routing d imension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs (100 ohm differential traces) 33 ohm 1 rs (85 ohm differential traces) 27 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 dif reference clock lp-hcsl differential output l1 l1' rs l2 l2' rs l4' l4 pci express down device ref_clk input figure 1: down device routing lp-hcsl differential output l1 l1' rs l2 l2' rs l4' l4 pci express add-in board ref_clk input figure 2: pci express connector routing
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 15 9ZXL1530 rev c 031312 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 3) pcie device ref_clk input figure 3 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 16 9ZXL1530 rev c 031312 marking diagram notes: 1. ?l? denotes rohs compliant package. 2. ?coo?: country of origin. 3. yyww is the last two digits of the year and week that the part was assembled. ics 9ZXL1530bkl lot coo yyww
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 17 9ZXL1530 rev c 031312 package outline and package dimensions (64-pin mlf) ordering information "lf" suffix to the part number are the pb -free configuration and are rohs compliant. ?b? is the device revision designator (will not correlate with th e datasheet revision). while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 9ZXL1530bklf see page 16 trays 64-pin mlf 0 to +70 c 9ZXL1530bklft tape and reel 64-pin mlf 0 to +70 c millimeters symbol min max a0.81.0 a1 0 0.05 a3 0.25 reference b 0.18 0.30 e 0.50 basic d x e basic 9.00 x 9.00 d2 min./max. 6.00 6.25 e2 min./max. 6.00 6.25 l min./max. 0.30 0.50 n64 n d 16 n e 16 anvil singulation -- or -- sawn singulation 1 2 n e d index area top view seating plane a3 a1 c a l e2 e2 2 d2 d2 2 e c 0.08 (ref) n d & n e odd (ref) n d & n e even (n d -1)x (ref) e n 1 2 b thermal base (typ) if n d & n e are even (n e -1)x (ref) e e 2
9ZXL1530 15-output low power differential zbuffer for pcie gen3 and qpi idt? 15-output low power differential zbuffer for pcie gen3 and qpi 18 9ZXL1530 rev c 031312 revision history rev. issuer issue date description page # 0.1 rdw 8/31/2010 initial release a rdw 4/18/2011 1. update electrical tables with characterization data and corrected minor typos 2. added test load information 3. updated ordering information and also corrected table to show bulk parts ship in trays, not tubes. 4. added mark information. 5-10, 15,16 b rdw 12/8/2011 1. updated tdspo_byp parameter by removing duplicate entry 2. updated rev id in byte 5 to indicate b rev 8, 13 c rdw 3/12/2012 1. corrected minor typos, standardized output type references to lp- hcsl. 2. added pin description for pin 37. 1,4,9,10, 14
? 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp pcclockhelp@idt.com innovate with idt and accelerate your future netw orks. contact: www.idt.com 9ZXL1530 15-output low power differential zbuf fer for pcie gen3 and qpi synthesizers

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